1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a bipolar transistor to be fabricated in self-aligned fashion and a method of fabricating such a transistor.
2. Description of the Related Art
With LSI recently having been improved to have a higher performance, a bipolar transistor with a higher performance; in particular, a bipolar transistor with a higher operation rate is needed. To accomplish such a request, it is material to reduce parasitic capacity and/or parasitic resistance in a bipolar transistor. Various self-align techniques have been proposed to do so, but these techniques simultaneously cause a method of fabricating a bipolar transistor to be more complicated and also cause the number of fabrication steps to increase.
Hereinbelow is explained a conventional method of fabricating a bipolar transistor in a self-aligned fashion, with reference to FIGS. 1A to 1F.
As illustrated in FIG. 1A, an n-type buried layer 2 is formed in a desired region in a p-type semiconductor substrate 14. An n-type epitaxial layer 1 is grown over the semiconductor substrate 14, and then, there are formed trench-type isolation regions 3 defining a region therebetween in which a semiconductor device is to be formed.
Then, there is deposited a silicon dioxide film 4 over the resultant, and an opening BE is formed in the silicon dioxide film 4 by means of photolithography at a region where a base and emitter are to be formed. Then, a silicon dioxide film 4a is formed within the opening BE. The silicon dioxide film 4a is thinner than the first formed silicon dioxide film 4. Then, an opening C is formed by means of photolithography at a region where a collector electrode is to be formed, as illustrated in FIG. 1B.
Then, the polysilicon film 5 is deposited all over a resultant structure by means of chemical vapor deposition (CVD), as illustrated in FIG. 1C. Then, ion implantation is carried out in selected regions by means of photolithography. Specifically, boron (B), one of p-type impurities, is implanted into a region where a base is to be formed, and phosphorus (P), one of n-type impurities, is implanted into a region where a collector electrode is to be formed, as illustrated in FIG. 1C. Then, photolithography and etching are carried out to thereby remove the polysilicon film 5 at regions other than regions where a base/emitter and a collector electrode are to be formed. Namely, the polysilicon film 5 now exists only at regions where a base/emitter and a collector electrode are to be formed. Then, the semiconductor substrate is thermally annealed to thereby make phosphorus contained in the polysilicon layer 5 diffuse into the n-type epitaxial layer 1 to the buried layer 2 in a region where a collector electrode is to be formed. Thus, a collector region 6 is formed, as illustrated in FIG. 1D.
Then, a silicon nitride film 7 is deposited over the resultant structure by means of CVD, and there is formed an opening 7a so that the thin silicon dioxide film 4a is exposed in a region where a base is to be formed, as illustrated in FIG. 1E. Then, an exposed portion of the thin silicon dioxide film 4a and a portion of the silicon dioxide film 4a located just below ends of the polysilicon film 5 are etched for removal with weak hydrofluoric acid to thereby form undercut hollow portions below the polysilicon film 5. Then, a polysilicon film 8 is deposited in the opening 7a by CVD so that the undercut hollow portions are filled therewith. Then, the thus deposited polysilicon film 8 is etched out so that the polysilicon film 8 exists only in the undercut hollow portions.
Then, boron ions are implanted into the epitaxial layer 1 through the opening 7a, followed by thermal annealing, to thereby form a base region 11 in the epitaxial layer 1. Then, an insulating film 9 is deposited over the resultant structure, and is anisotropically etched so that the insulating film 9 exists only on an inner sidewall of the opening 7a. Then, an n-type polysilicon film 10 is formed, and is patterned to cover the opening 7a, as illustrated in FIG. 1F. Then, the semiconductor substrate is thermally annealed to thereby make impurities contained in the n-type polysilicon film 10 diffuse into the base region 11 to thereby form an emitter region 13. The above mentioned thermal annealing carried out for the formation of the base region 11 makes p-type impurities contained in the polysilicon film 5 diffuse into the n-type epitaxial layer 1 through the polysilicon film 8 to thereby form external base regions 12.
The above mentioned conventional method needs seven photolithography steps to be carried out after the formation of the device isolation regions 3 in order to fabricate a bipolar transistor: (1) first for forming the opening BE in the silicon dioxide film 4 at a region where base/emitter are to be formed; (2) second for forming the opening C in the silicon dioxide film 4 at a region where a collector electrode is to be formed; (3) third for carrying out p-type impurities ion implantation into the polysilicon film 5 at a region where a base electrode is to be formed; (4) fourth for carrying out n-type impurities ion implantation into the polysilicon film 5 at a region where the collector region 6 is to be formed; (5) fifth for patterning the polysilicon film 5; (6) sixth for forming the base opening 7a through the silicon nitride film 7 and the polysilicon film 5; and (7) seventh for patterning the polysilicon film 10.
As mentioned above, the conventional method of fabricating a bipolar transistor in self-aligned fashion needs a lot of photolithography steps to be carried out, which increases the number of fabrication steps and lengthens the term for fabrication of a bipolar transistor. In addition, the increased number of fabrication steps is accompanied with problems of reduction in fabrication yield and increased fabrication cost.